fn4520 rev 5.00 page 1 of 10 september 2000 fn4520 rev 5.00 september 2000 hi5628 8-bit, 125/60msps, dual high s peed cmos d/a converter datasheet the hi5628 is an 8- bit, dual 125msps d/a converter which is implemented in an advanc ed cmos process. operating from a single +5v to +3v sup ply, the converter provides 20.48ma of full scale output current and includes an input data register. low glitch e nergy and excellent frequency domain performance are achi eved using a segmented architecture. the single dac version is the hi5660 while 10-bit versions exist in the hi5760 and hi5728. features ? throughput rate . . . . . . . . . . . . . . . . . . . . . . . 125msps ? low power . . . . . . . . . . . . . 330mw at 5v, 170mw at 3v ? integral linearity error . . . . . . . . . . . . . . . . . . . ? 0.25 lsb ? differential linearity . . . . . . . . . . . . . . . . . . . . . ? 0.25 lsb ? channel isolation (typ) . . . . . . . . . . . . . . . . . . . . . . 80db ? sfdr to nyquist at 10mhz output . . . . . . . . . . . . 60dbc ? internal 1.2v bandgap voltage reference ? single power supply from +5v to +3v ? cmos compatible inputs ? excellent spurious free dynamic range applications ? direct digital frequency synthesis ? wireless communications ? signal reconstruction ? arbitrary waveform generators ? test equipment ? high resolution imaging systems pinout hi5628 (lqfp) top view ordering information part number temp. range ( o c) package pkg. no. max clock speed hi5628in -40 to 85 48 ld lqfp q48.7x7a 125mhz hi5628/6in -40 to 85 48 ld lqfp q48.7x7a 60mhz hi5628eval1 25 evaluation platform 125mhz 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 qd4 qd3 qd2 qd1 qd0 (lsb) dgnd dgnd dv dd dgnd nc av dd agnd id4 id3 id2 id1 id0 (lsb) sleep dv dd dgnd nc av dd dgnd dgnd id5 id6 id7 (msb) dv dd dgnd qclk dgnd dv dd qd7 (msb) qd6 qd5 iclk agnd icomp1 reflo iouta ioutb agnd agnd qoutb qouta fsadj refio qcomp1 n o t r e c o m m e n d e d f o r n e w d e s i g n s n o r e c o m m e n d e d r e p l a c e m e n t c o n t a c t o u r t e c h n i c a l s u p p o r t c e n t e r a t 1 - 8 8 8 - i n t e r s i l o r w w w . i n t e r s i l . c o m / t s c
hi5628 fn4520 rev 5.00 page 2 of 10 september 2000 typical applications circuit note: recommended separate analog and digital ground planes, con nected at a single point near the device. see an9827. ioutb iouta 50 ? +5v to +3v (supply) 0.1 ? f 50 ? 10 ? f 50 ? 0.1 ? f 1.91k ? ferrite 10 ? h + bead r set 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 av dd id5 id4 id3 id6 id7 (msb) qd7 (msb) id2 id1 id0 (lsb) qd6 qd5 qd4 qd3 qd2 qd1 qd0 (lsb) i clk /q clk dv dd 0.1 ? f dv dd sleep dv dd 0.1 ? f dvdd dgnd nc (ground) av dd agnd icomp1 0.1 ? f 0.1 ? f agnd qouta qoutb 50 ? 50 ? 0.1 ? f refio qcomp1 0.1 ? f av dd 0.1 ? f av dd agnd av dd nc (gnd) 0.1 ? f dv dd dgnd dvdd dgnd dgnd dgnd dgnd analog ground plane digital ground plane plane av dd note: icomp1 and q comp1 pins (24, 14) must be tied tog ether externally dv dd 10 ? f 0.1 ? f ferrite 10 ? h bead +5v to +3v power supply (power plane) (power plane)
hi5628 fn4520 rev 5.00 page 3 of 10 september 2000 functional block diagram upper voltage reference (lsb) id0 id1 id2 id3 id4 id5 id6 iclk (msb) id7 5-bit decoder refio latch av dd agnd dv dd dgnd latch cascode current source switch matrix bias generation int/ext fsadj reference int/ext select reflo 31 34 34 31 msb segments 3 lsbs + icomp1 sleep iouta ioutb upper (lsb) qd0 qd1 qd2 qd3 qd4 qd5 qd6 qclk (msb) qd7 5-bit decoder latch latch cascode current source switch matrix 31 34 34 31 msb segments 3 lsbs + qcomp1 qouta qoutb
hi5628 fn4520 rev 5.00 page 4 of 10 september 2000 absolute maximum ratings thermal information digital supply voltage dv dd to dcom . . . . . . . . . . . . . . . . . +5.5v analog supply voltage av dd to acom . . . . . . . . . . . . . . . . . +5.5v grounds, acom to dcom . . . . . . . . . . . . . . . . . . . -0.3v to +0.3v digital input voltages (d7-d0, clk, sleep). . . . . . . . dv dd + 0.3v internal reference output current. . . . . . . . . . . . . . . . . . . . . ? 50 ? a reference input voltage range. . . . . . . . . . . . . . . . . . av dd + 0.3v analog output current (i out ) . . . . . . . . . . . . . . . . . . . . . . . . . 24ma operating conditions temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . -40 o c to 85 o c thermal resistance (typical, note 1) ? ja ( o c/w) lqfp package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . .150 o c maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . .300 o c caution: stresses above those listed in ?abs olute maximum ratings? may cause permanent dam age to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ? ja is measured with the component mounted on an evaluation pc boa rd in free air. electrical specifications av dd = +5v, dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for pow er supply characteristics. parameter test conditions hi5628in t a = -40 o c to 85 o c units min typ max system performance (per channel) resolution 8- -bits integral linearity error, inl best fit straight line (note 7) - 0.5 ? 0.25 +0.5 lsb differential linearity error, dnl (note 7) -0.5 ? 0.25 +0.5 lsb offset error, i os (note 7) -0.025 - +0.025 % fsr offset drift coefficient (note 7) - 0.1 - ppm fsr/ o c full scale gain error, fse with external reference (notes 2, 7) - 10 ? 2+10% fsr with internal reference (notes 2, 7) -10 ? 1+10% fsr full scale gain drifta with external reference (note 7) - ? 50 - ppm fsr/ o c with internal reference (note 7) - ? 100 - ppm fsr/ o c gain matching between channels -0.5 0.1 0.5 db i/q channel isolation f out = 10mhz - 80 - db output voltage compliance range (note 3) -0.3 - 1.25 v full scale output current, i fs 2-20ma dynamic characteristics (per channel) clock rate, f clk (note 3, 9) 125 - - mhz output settling time, (t sett ) 0.8% ( ? 1 lsb, equivalent to 7 bits) (note 7) - 5 - ns 0.4% ( ? 1/2 lsb, equivalent to 8 bits) (note 7) - 15 - ns singlet glitch area (peak glitch) r l = 25 ?? (note 7) - 5 - pv?s output rise time full scale step - 1.5 - ns output fall time full scale step - 1.5 - ns output capacitance -10- pf output noise ioutfs = 20ma - 50 - pa/ ? hz ioutfs = 2ma - 30 - pa/ ? hz
hi5628 fn4520 rev 5.00 page 5 of 10 september 2000 ac characteristics - hi5628in - 125mhz (per channel) spurious free dynamic range, sfdr within a window f clk = 125msps, f out = 32.9mhz, 10mhz span (notes 4, 7) - 70 - dbc f clk = 100msps, f out = 5.04mhz, 4mhz span (notes 4, 7) - 73 - dbc total harmonic distorti on (thd) to nyquist f clk = 100msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc spurious free dynamic range, sfdr to nyquist f clk = 125msps, f out = 32.9mhz, 62.5mhz span (notes 4, 7) - 51 - dbc f clk = 125msps, f out = 10.1mhz, 62.5mhz span (notes 4, 7) - 61 - dbc f clk = 100msps, f out = 40.4mhz, 50mhz span (notes 4, 7) - 48 - dbc f clk = 100msps, f out = 20.2mhz, 50mhz span (notes 4, 7) - 56 - dbc f clk = 100msps, f out = 5.04mhz, 50mhz span (notes 4, 7) - 68 - dbc f clk = 100msps, f out = 2.51mhz, 50mhz span (notes 4, 7) - 68 - dbc ac characteristics - hi5628/6in - 60mhz (per channel) spurious free dynamic range, sfdr within a window f clk = 60msps, f out = 10.1mhz, 10mhz span (notes 4, 7) - 70 - dbc f clk = 50msps, f out = 5.02mhz, 2mhz span (notes 4, 7) - 73 - dbc f clk = 50msps, f out = 1.00mhz, 2mhz span (notes 4, 7) - 74 - dbc total harmonic distorti on (thd) to nyquist f clk = 50msps, f out = 2.00mhz (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 1.00mhz (notes 4, 7) - 68 - dbc spurious free dynamic range, sfdr to nyquist f clk = 60msps, f out = 20.2mhz, 30mhz span (notes 4, 7) - 54 - dbc f clk = 60msps, f out = 10.1mhz, 30mhz span (notes 4, 7) - 60 - dbc f clk = 50msps, f out = 20.2mhz, 25mhz span (notes 4, 7) - 53 - dbc f clk = 50msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 67 - dbc f clk = 50msps, f out = 2.51mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 50msps, f out = 1.00mhz, 25mhz span (notes 4, 7) - 68 - dbc f clk = 25msps, f out = 5.02mhz, 25mhz span (notes 4, 7) - 71 - dbc voltage reference internal reference voltage, v fsadj voltage at pin 22 with internal reference 1.04 1.16 1.28 v internal reference voltage drift - ? 60 - ppm / o c internal reference output current sink/source capability - 0.1 - ? a reference input impedance -1-m ? reference input multiplying bandwidth (note 7) - 1.4 - mhz digital inputs d7-d0, clk (per channel) input logic high voltage with 5v supply, v ih (note 3) 3.5 5 - v input logic high voltage with 3v supply, v ih (note 3) 2.1 3 - v input logic low voltage with 5v supply, v il (note 3) - 0 1.3 v input logic low voltage with 3v supply, v il (note 3) - 0 0.9 v input logic current, i ih -10 - +10 ? a input logic current, i il -10 - +10 ? a digital input capacitance, c in -5-pf electrical specifications av dd = +5v, dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for pow er supply characteristics. (continued) parameter test conditions hi5628in t a = -40 o c to 85 o c units min typ max
hi5628 fn4520 rev 5.00 page 6 of 10 september 2000 timing characteristics (per channel) data setup time, t su see figure 3 (note 3) 3 - - ns data hold time, t hld see figure 3 (note 3) 3 - - ns propagation delay time, t pd see figure 3 - 1 - ns clk pulse width, t pw1 , t pw2 see figure 3 (note 3) 4 - - ns power supply characteristics av dd power supply (note 8, 9) 2.7 5.0 5.5 v dv dd power supply (note 8, 9) 2.7 5.0 5.5 v analog supply current (i avdd ) 5v or 3v, ioutfs = 20ma - 46 60 ma 5v or 3v, ioutfs = 2ma - 8 - ma digital supply current (i dvdd ) 5v, ioutfs = dont care (note 5) - 6 10 ma 3v, ioutfs = dont care (note 5) - 3 - ma supply current (i avdd ) sleep mode 5v or 3v, ioutfs = dont care) - 3.2 6 ma power dissipation (both channels) 5v, ioutfs = 20ma (note 6) - 330 -mw 5v, ioutfs = 2ma (notes 6) - 140 - mw 3v, ioutfs = 20ma (note 6) - 170 - mw 3v, ioutfs = 2ma (note 6) - 54 - mw 5v, ioutfs = 20ma (note 10) - 300 - mw 3.3v, ioutfs = 20ma (note 10) - 150 - mw 3v, ioutfs = 20ma (note 10) - 135 - mw power supply rejection single supply (note 7) -0.2 - +0.2 % fsr/v notes: 2. gain error measured as the error in the ratio between the ful l scale output current and the current through r set (typically 625 ? a). ideally the ratio should be 32. 3. parameter guaranteed by design or characterization and not pr oduction tested. 4. spectral measurements made wi th differential transformer coup led output and no filtering. 5. measured with the clock at 50msps and the output frequency at 1mhz, both channels. 6. measured with the clock at 100msps and the output frequency a t 40mhz, both channels. 7. see definition of specifications. 8. for operation below 3v, it is recommended that the output cur rent be reduced to 12ma or less to maintain optimum performance . dv dd and av dd do not have to be equal. 9. for operation above 125mhz, it is recommended that the power supply be 3.3v or greater. the part is functional with the cloc k above 125msps and the power supply below 3.3v, but performance is degraded. 10. measured with the clock at 60msps and the output frequency a t 10mhz, both channels. electrical specifications av dd = +5v, dv dd = +5v, v ref = internal 1.2v, ioutfs = 20ma, t a = 25 o c for all typical values. data given is per channel except for pow er supply characteristics. (continued) parameter test conditions hi5628in t a = -40 o c to 85 o c units min typ max
hi5628 fn4520 rev 5.00 page 7 of 10 september 2000 timing diagrams figure 1. output settling time diagram figure 2. peak glitch area (singlet) measurement method figure 3. propagation delay, setup time, hold time and minimum p ulse width diagram clk d7-d0 i out 50% t sett 1 / 2 lsb error band t pd v t(ps) height (h) width (w) glitch area = 1 / 2 (h x w) clk d7-d0 i out 50% t pw1 t pw2 t su t hld t su t su t pd t pd t pd t hld t hld t sett t sett t sett
hi5628 fn4520 rev 5.00 page 8 of 10 september 2000 definition of specifications integral linearity error, inl , is the measure of the worst case point that deviates from a best fi t straight line of data value s along the transfer curve. differential linearity error, dnl, is the measure of the step size output deviation from code to code. ideally the step size should be 1 lsb. a dnl spe cification of 1 lsb or less guarantees monotonicity. output settling time, is the time required for the output voltage to settle to within a specified error band measured fro m the beginning of the output tr ansition. the m easurement was done by switching from code 0 to 64, or quarter scale. termination impedance was 25 ? due to the parallel resistance of the output 50 ? and the oscilloscopes 50 ? input. this also aids the ability to resolve the specified error band without overdriving the oscilloscope. singlet glitch area, is the switching tran sient appearing on the output during a code transition. it is measured as the area under the overshoot portion of the curve and is expressed as a volt-time specification. full scale gain error , is the error from a n ideal ratio of 32 between the output current and the full scale adjust current (through r set ). full scale gain drift, is measured by setting the data inputs to all ones and measuring the out put voltage through a known resistance as the tempera ture is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per degree c. total harmonic distortion, thd , is the ratio of the dac output fundamental to the rms sum of the first five harmonics. spurious free dynamic range, sfdr , is the amplitude difference from the fundamental to the largest harmonically or non-harmonically related spur within the specified window. output voltage compliance range, is the voltage limit imposed on the output. the output impedance load should be chosen such that the voltage d eveloped does not violate the compliance range. offset error, is measured by setting t he data inputs to all zeros and measuring the outp ut voltage through a known resistance. offset error is defined as the maximum deviation of the output current from a value of 0ma. offset drift, is measured by setting the data inputs to all zeros and measuring the output voltage through a known resistance as the temperature is varied from t min to t max . it is defined as the maximum deviation from the value measured at room temperature to the value measured at either t min or t max . the units are ppm of fsr (full scale range) per degree c. power supply rejection, is measured using a single power supply. its nominal +5v is varied ? 10% and the change in the dac full scale output is noted. reference input multiplying bandwidth, is defined as the 3db bandwidth of the voltage r eference input. it is measured by using a sinusoidal waveform as the external reference with the digital inputs set to all 1s. the freq uency is increased un til the amplitude of the output waveform is 0 .707 of its original value. internal reference voltage drift, is defined as the maximum deviation from the value measured at room te mperature to the value measured at either t min or t max . the units are ppm per degree c. detailed description the hi5628 is a dual, 8-bit, cu rrent out, cmos, digital to analog converter. its maximum update rate i s 125msps and can be powered by either single or dual power supplies in the recommended range of +3v to +5 v. it consumes less than 330mw of power when using a +5v supply with the data switching at 100msps. the a rchitecture is based on a segmented current source arrang ement that reduces glitch by reducing the amount of current s witching at any one time. the five msbs are represented by 31 major current sources of equivalent current. the three lsbs are comprised of binary weighted current sources. consi der an input pattern to the converter which ramps through all the codes from 0 to 255. the three lsb current sources would begin to count up. when they reached the all high state (decimal value of 7) and needed to count to the next code, they w ould all turn off and the firs t major current source would turn on. to continue counting upward, the 3 lsbs would count up another 7 codes, and then the next major current source would turn on and the three lsbs would all turn off. the pr ocess of the sing le, equivalent, major current source turning on and the three l sbs turning off each time the conv erter reaches another 7 codes greatly reduces the glitch a t any one switching point. in previous architectures that contained all binary weighted current sources or a binary weighted r esistor ladder, the converter might have a substantially larger amount of current turning on and off at certain, worst-case transition points such as midscale and quarter scale transitions. by greatly reducing the amount of current switching at c ertain major transitions, the overall glitch of the convert er is dramatically reduced, improving settling times and transient problems.
hi5628 fn4520 rev 5.00 page 9 of 10 september 2000 digital inputs and termination the hi5628 digital inputs are guaranteed to cmos levels. however, ttl compatibility can be achieved by lowering the supply voltage to 3v due to the digital threshold of the input buffer being approximately hal f of the supply voltage. the internal register is updated on the rising edge of the clock. t o minimize reflections, proper termination should be implemented. if the lines driving the clock and the digital inputs are 50 ? lines, then 50 ? termination resistors should be placed as close to the converter inputs as possible, c onnected to the digital ground plane (if separate grounds are used). ground plane(s) if separate digital and analog ground planes are used, then all of the digital functions of the device and their corresponding components should be over the digital ground plane and terminated to the digital ground plane. the same is true for th e analog components and the analog ground plane. the converter will function properly with a single ground plane, as the evaluation board is configured in this matter. noise reduction to minimize power supply noise, 0.1 ? f capacitors should be placed as close as possible to the converters power supply pins, av dd and dv dd . also, should the layout be designed using separate digital and analog ground planes, these capacitors should be terminated to the digital ground for dv dd and to the analog ground for av dd . additional filtering of the power supplies on the board is recommended. voltage reference the internal voltage reference of the device has a nominal valu e of +1.2v with a ? 60 ppm/ o c drift coefficient over the full temperature rang e of the converter. it is recommended that a 0.1 ? f capacitor be place d as close as possible to the refio pin, connected to the anal og ground. the reflo pin (15) selects the reference. the internal referenc e can be selecte d if pin 15 is tied low (ground). if an external refer ence is desired, then pin 15 should be tied high (to the analog supply voltage) and the exte rnal reference driven into refio, pin 23. the full scale output curr ent of the converter is a function o f the voltage ref erence used an d the value of r set . i out should be within the 2ma to 20ma range, through operation below 2ma i s possible, with performance degradation. if the internal reference is used, v fsadj will equal approximately 1.16v (pin 22). if an external reference is used, v fsadj will equal the external reference. the calculation for i out (full scale) is: i out (full scale) = (v fsadj /r set )x 32. if the full scale output current is set to 20ma by using the in ternal voltage reference (1.16v) and a 1.86k ? r set resistor, then the input coding to out put current will resemble the following: outputs iouta and ioutb (or qo uta and qoutb) are complementary current outputs. the sum of the two currents is always equal to the full scale out put current minus one lsb. if single ended use is desired, a load resistor can be used to convert the output current to a voltage. it is recommended that the unused outpu t be either grounded or equally terminated. the voltage developed at the output must not violate the output voltage compliance range of -0.3v to 1.25v. r load should be chosen so that the desired out put voltage is produced in conjunction with the output f ull scale current, which is described above in the refere nce section. if a known line impedance is to be driven, then the output load resistor should be chosen to match this im pedance. the output voltage equation is: v out = i out x r load . these outputs can be used in a different ial-to-single-ended arrangement to achieve better harmonic rejection. the sfdr measurements in this data sheet were performed with a 1:1 transformer on the o utput of the dac (see figure 1). with the center tap grounded, the output swing of pins 16 and 17 will be biased at zero volts. it is impo rtant to note here that the negative voltage output complia nce range limit is -300mv, imposing a maximum of 600mv p-p amplitude with this configuration. the loading as s hown in figure 1 will result in a 500mv signal at the output of the transformer if the full scale output current of the dac is set to 20ma. v out = 2 x i out x r eq , where r eq is ~12.5 ? . allowing the center tap to float will result in identical transformer output, however the output pins of the dac will have positive dc offset. the 50 ? load on the output of the transformer represents the spectrum analyzers input impedance. table 1. input coding vs output current input code (d7-d0) iouta (ma) ioutb (ma) 1111 1111 20 0 1000 0000 10 10 0000 0000 0 20 pin 17 (20) pin 16 (21) v out = (2 x i out x r eq )v 100 ? 50 ? 50 ? 50 ? ioutb (qoutb) iouta (qouta) figure 4.
fn4520 rev 5.00 page 10 of 10 september 2000 hi5628 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2000-2004. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. pin descriptions pin no. pin name pin description 39-32 qd7 (msb) through qd0 (lsb) digital data bit 7, the most significant bit through digital da ta bit 0, the least significant bit, of the q channel. 1-5, 48-46 id7 (msb) through id0 (lsb) digital data bit 7, the most sig nificant bit through digital da ta bit 0, the least significant bit, of the i channel. 8 sleep control pin for power-down mode. sleep mode is active hig h; connect to ground for normal mode. sleep pin has internal 20 ? a active pulldown current. 15 reflo connect to analog ground to enable internal 1.2v referen ce or connect to av dd to disable. 23 refio reference voltage input if internal reference is disable d and reference voltage output if internal reference is enabled. use 0.1 ? f cap to ground when internal reference is enabled. 22 fsadj full scale current adjust. use a resistor to ground to a djust full scale output current. full scale output current per channel = 32 x i fsadj . 14, 24 icomp1, qcomp1 reduces noise. connect each to av dd with 0.1 ? f capacitor. the icomp1 and qcomp1 pins must be tied together externally. 13, 18, 19, 25 agnd analog ground connections. 17 ioutb the complementary current output of the i channel. bits set to all 0s gives full scale current. 16 iouta current output of the i channel. bits set to all 1s give s full scale current. 20 qoutb the complementary current output of the q channel. bits set to all 0s gives full scale current. 21 qouta current output of the q channel. bits set to all 1s give s full scale current. 11, 27 nc no connect. recommended: connect to ground. 12, 26 av dd analog supply (+2.7v to +5.5v). 6, 7, 10, 28, 30, 31, 41, 44 dgnd digital ground. 9, 29, 40, 45 dv dd supply voltage for digital ci rcuitry (+2.7v to +5.5v). 43 iclk clock input for i channel. p ositive edge of clock latches data. 42 qclk clock input for q channel. positive edge of clock latches data.
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